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W83L784R winbond h/w monitoring ic
w83l 784r preliminary publication release date: oct. 1999 - 1 - revision 0.55 W83L784R data sheet revision history pages dates version version on web main contents 1 n.a. n.a. all the version before 0.50 are for internal use. 2 n.a. 99/4 0.5 n.a. first publication. 3 p.56 - 57 99/6 0.52 n.a. schematics updated 4 p.56 99/6 0.53 n.a. corrected the length (d) from 10.2mm to 7.2mm in the package outline table. 5 p.57 99/9 0.54 n.a. updated v0.5 schematics adding pull - high resistors for reset# (pin15) 6 p.36 p. 9 99/10 0.55 n.a. this update is for c version ic. update cr[54h] register for pwmout function. change pin 15 from output to open - drain. 7 8 please note that all data and specifications are subject to change without notice. all the trade marks of products and com panies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to res ult in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.
w83l 784r preliminary publication release date: oct. 1999 - 2 - revision 0.55 table of contents 1. general description ................................ ................................ ................................ .................... 5 2. features ................................ ................................ ................................ ................................ .............. 6 2.1 m onitoring i tems ................................ ................................ ................................ ................................ 6 2.2 a ctions e nabling ................................ ................................ ................................ ................................ 6 2.3 p ower g ood ................................ ................................ ................................ ................................ ......... 6 2.4 g eneral ................................ ................................ ................................ ................................ ............... 6 2.5 p ackage ................................ ................................ ................................ ................................ ................ 6 3. key specifications ................................ ................................ ................................ ........................ 7 4. pin configuration ................................ ................................ ................................ ......................... 7 5. pin description ................................ ................................ ................................ ................................ 8 6. fu nctional description ................................ ................................ ................................ ........... 10 6.1 g eneral d escription ................................ ................................ ................................ ......................... 10 6.2 a ccess i nterface ................................ ................................ ................................ ............................... 10 6.2.1 the first serial bus access timing are shown as follow: ................................ ................................ . 10 6.2.2 the serial bus timing of the temperature cput1 and cput2 is shown as follow: ........................ 11 6.3 a nalog i nputs ................................ ................................ ................................ ................................ ... 15 6.3.1 monitor over 4.096v voltage: ................................ ................................ ................................ ...... 15 6.3.2 power good for 3v and 5v ................................ ................................ ................................ ........... 16 6.3.3 battery fault alarm ................................ ................................ ................................ ..................... 17 6.4 t emperature m easurement m achine ................................ ................................ .............................. 17 6.4.1 monitor temperature from thermistor: ................................ ................................ .......................... 17 6.4.2 monitor temperature from pentium ii tm thermal diode or bipolar transistor 2n3904 ................... 17 6.4.3 over temperature ................................ ................................ ................................ ........................ 18 6.5 fan s peed c ount and fan s peed c ontrol ................................ ................................ ..................... 20 6.5.1 fan speed count ................................ ................................ ................................ ........................... 20 6.5.2 fan speed control ................................ ................................ ................................ ........................ 21 6.5.3 smart fan control ................................ ................................ ................................ ....................... 22 6.5.4 fan fault alarm ................................ ................................ ................................ .......................... 24 6.6 smi# ................................ ................................ ................................ ................................ ................... 24 6.6.1 temperature ................................ ................................ ................................ ................................ . 24 6.6.2 voltage ................................ ................................ ................................ ................................ ........ 26 6.6.3 fan ................................ ................................ ................................ ................................ .............. 26 7. registers and ram ................................ ................................ ................................ ....................... 27 7.1 c onfiguration r egister ? i ndex 40 h ................................ ................................ .............................. 27 7.2 i nterrupt s tatus r egister 1 ? i ndex 41 h ................................ ................................ ........................ 27 7.3 i nterrupt s tatus r egister 2 ? i ndex 42 h ................................ ................................ ....................... 28 7.4 smi m ask r egister 1 ? i ndex 43 h ................................ ................................ ................................ ... 28
w83l 784r preliminary publication release date: oct. 1999 - 3 - revision 0.55 7.5 smi y m ask r egister 2 ? i ndex 44 h ................................ ................................ ................................ 29 7.6 r eal t ime h ardware s tatus r egister i -- i ndex 45 h ................................ ................................ ...... 29 7.7 r eal t ime h ardware s tatus r egister ii -- i ndex 46 h ................................ ................................ ..... 30 7.8 r eserved r egister -- i ndex 47 h - 48 h ................................ ................................ ................................ 30 7.9 f an d ivisor r egister ? i ndex 49 h ................................ ................................ ................................ ... 30 7.10 s erial b us a ddress ( for v oltage ,f an , and internal tempera ture ) r egister ? a ddress 4a h 31 7.11 cput1 t emperatur e and cput2 t emperature s erial b us a ddress r egister -- i ndex 4b h ......... 31 7.12 w inbond v endor id (l ow b yte ) - i ndex 4c h (a uto i ncrease ) ................................ ...................... 32 7.13 w inbond v endor id (h igh b yte ) - i ndex 4d h (n o a uto i ncreas e ) ................................ ................ 32 7.14 c hip id -- i ndex 4e h ................................ ................................ ................................ ........................... 32 7.15 acpi t emperature i ncrement r egister -- i ndex 4f h ................................ ................................ ..... 32 7.16 ovt# p roperty s elect - i ndex 50 h ................................ ................................ ................................ .. 33 7.1 7 smi# p roperty s elect -- i ndex 51 h ................................ ................................ ................................ .. 34 7.18 fanin1/gpo1, fanin2/gpo2 and beep/gpo3 c ontrol r egister - i ndxe 52 h ............................ 34 7.19 cput1/cput2 t hermal s ensor t ype r egister -- i ndex 53 h ................................ .......................... 36 7.20 m isc c ontrol r egister -- i ndex 54 h ................................ ................................ ................................ 36 7.21 f an /vbat f ault c ontrol r egister -- i ndex 55 h ................................ ................................ ............ 37 7.22 f an 1 f ault h igh l imit c ount -- i ndex 56 h ................................ ................................ ..................... 37 7.23 f an 2 f ault l ow l imit c ount -- i ndex 57 h ................................ ................................ ...................... 37 7.24 f an 2 f ault h igh l imit c ount -- i ndex 58 h ................................ ................................ ..................... 37 7.25 f an 1 f ault l ow l imit c ount -- i ndex 59 h ................................ ................................ ...................... 38 7.26 vbat f ault h igh l imit v alue -- i ndex 5a h ................................ ................................ .................... 38 7.27 vbat f ault l ow l imit v alue -- i ndex 5b h ................................ ................................ ..................... 38 7.28 fan 1 p re - s cale r egister -- i ndex 80 h ................................ ................................ ............................ 38 7.29 fan 1 d uty c ycle s elect r egister -- 81 h ( b ank 0 ) ................................ ................................ ......... 39 7.30 fan 2 p re - s cale r egister -- i ndex 82 h ................................ ................................ ............................ 39 7.31 fan2 d uty c ycle s elect r egister -- i ndex 83 h ................................ ................................ .............. 39 7.32 fan c onfiguration r egister -- i ndex 84 h ................................ ................................ ....................... 40 7.33 cput1 t arget t emperature r egister / f an 1 t arget s peed r egister -- i ndex 85 h ...................... 40 7.34 cput2 t arget t emperature r egister / f an 2 t arget s peed r egister -- i ndex 86 h ...................... 41 7.35 t olerance o f t arget t emperature or t arget s peed r egister -- i ndex 87 h ................................ 41 7.36 f an 1 pwm s top d uty c ycle r egister -- i ndex 88 h ................................ ................................ ....... 42 7.37 f an 2 pwm s top d uty c ycle r egister -- 89 h ( b ank 0 ) ................................ ................................ .... 42 7.38 f an 1 s tart - up d uty c ycle r egister -- i ndex 8a h ................................ ................................ ......... 42 7.39 f an 2 s tart - up d uty c ycle r egister -- i ndex 8b h ................................ ................................ .......... 42 7.40 f an 1 s top t ime r egister -- i ndxe 8c h ................................ ................................ ............................. 43 7.41 f an 2 s top t ime r egister -- i ndex 8d h ................................ ................................ ............................. 43 7.42 f an s tep d own t ime r egister -- i ndex 8e h ................................ ................................ ...................... 43 7.43 f an s tep u p t ime r egister -- i ndex 8f h ................................ ................................ ............................ 43 7.44 t emperature s en sor 1 (i nternal t hermal d iode ) o ffset r egister - i ndex 90 h .......................... 44 7.45 t emperature s ensor 2 (cpu t1) o ffset r egister - i ndex 91 h ................................ ....................... 44 7.46 t emperature s ensor 3 (cpu t2) o ffset r egister - i ndex 92 h ................................ ....................... 45 8. value ram and limit value ................................ ................................ ................................ .... 45 8.1 v alue ram ? i ndex 20 h - 3f h or 60 h - 7f h ................................ ................................ ..................... 45 9. temperature sensor 2 (cpu t1) registers ................................ ................................ ........ 47
w83l 784r preliminary publication release date: oct. 1999 - 4 - revision 0.55 9.1 t emperatu re s ensor 2 t emperature r egister - i ndex 00 h ................................ ............................ 47 9.2 t emperature s ensor 2 c onfiguration r egister - i ndex 01 h ................................ ......................... 47 9.3 t emperature s ensor 2 h ysteresis r egister - i ndex 02 h ................................ ................................ 47 9.4 t emperature s ensor 2 o ver - temperature r egister - i ndex 03 h ................................ ................... 47 10. temperature sensor 3 (cpu t2) registers ................................ ................................ .... 48 10.1 t emperature s ensor 3 t emperature r egister - i ndex 00 h ................................ ............................ 48 10.2 t emperature s ensor 3 c onfiguration r egister - i ndex 01 h ................................ ......................... 48 10.3 t emperature s ensor 3 h ysteresis r egister - i ndex 02 h ................................ ................................ 48 10.4 t emperature s ensor 3 o ver - temperature r egister - i nd ex 03 h ................................ ................... 48 11. specifications ................................ ................................ ................................ ............................ 49 11.1 a bsolute m aximum r atings ................................ ................................ ................................ ............. 49 11.2 dc c haracteristics ................................ ................................ ................................ .......................... 49 11.3 ac c haracteristics ................................ ................................ ................................ .......................... 51 12. how to read the top marking ................................ ................................ .......................... 52 13. package drawing and dimensions ................................ ................................ .................. 53 14. W83L784R schematics ................................ ................................ ................................ ............... 54
w83l 784r preliminary publication release date: oct. 1999 - 5 - revision 0.55 1. general description W83L784R is an evolv ing product of w83782d --- winbond's most popular hardware status monitoring ic. specifically designed for the notebook system, W83L784R can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high - end notebook system to work stably and properly. an 8 - bit analog - to - digital converter (adc) was built inside W83L784R. the W83L784R can monitor 4 analog voltage inputs, 2 fan tachometer inputs, one on - chip internal temperature sensor and 2 remote temperature sensors. the remote temperature sensing can be performed by thermistors, or 2n3904 npn - type transistors, or directly from intel tm deschutes cpu thermal diode output. the W83L784R provides 2 pwm (pulse width modulation) outputs for the fan speed control to support the } thermal cruise tm ~ system, which can maintain the cpu or system in the specific programmable temperature under the hardware control. another fan speed control mode is } speed cru ise } to keep the fan operating in the specific r.p.m.. on the other hand, the W83L784R provides low active outputs such as fan fault and battery low which could issue the hardware warning signals when the fan speed or battery voltage drop out of the pres et range. also the W83L784R provides: power good reset for 3v and 5v; power down mode for power saving; fault pin for necessary h/w shutdown control; smi#, ovt#, gpo# signals for system protection events; i 2 c tm serial bus interface. through the applicat ion software or bios, the users can read all the monitored parameters of system from time to time. and a pop - up warning can be also activated when the monitored item was out of the proper/preset range. the application software could be winbond's hardware doctor tm , or intel tm ldcm (landesk client management), or other management application software. also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupt s. for the spacing saving consideration of the notebook system, W83L784R is in the package of 209mil 20pins - ssop.
w83l 784r preliminary publication release date: oct. 1999 - 6 - revision 0.55 2. features 2.1 monitoring items 2 thermal inputs from remote thermistors or 2n3904 npn - type transistors or pentium tm ii (deschutes) thermal diode output one on - chip temperature detection 4 voltage inputs --- typical for vcore, +3.3v, +5v, battery 2 sets of fan speed control and fan speed monitoring input watchdog comparison of all monitored values programmable hysteresis and setting point s (alarm thresholds) for all monitored items 2.2 actions enabling issue fan fault signal as fans are abnomally stopped issue battery low signal as bettery voltage is abnomally out of range 2 pwm (pulse width modulation) outputs for fan speed control to suppor t } thermal cruise tm ~ or } speed cruise tm ~ --- automatically maintain the cpu or system in the specific temperature or keep the fans in the specific speed under the h/w control issue smi#, ovt#, gpo to activate system protection pwr_dn# setting for th e power down mode warning signal pop - up in application software 2.3 power good issue reset# outputs as the power good signal when 3v and 5v rise across a reset threshold. 2.4 general i 2 c tm serial bus interface intel tm ldcm (dmi driver 2.0) support acer tm adm ( dmi driver 2.0) support winbond hardware monitoring application software (hardware doctor tm ) support, for both windows 95/98 meet wfm 2.0 (wired for management) spec. 5v vcc operation 2.5 package 20 - pin ssop (209mil)
w83l 784r preliminary publication release date: oct. 1999 - 7 - revision 0.55 3. key specifications voltage monitoring accuracy 1% (max) monitoring temperature range and accuracy - 40 c to +120 c 3 c(max) supply voltage 5v operating supply current 2 ma typ. power down suppy current 0.5 ma typ. adc resolution 8 bits 4. pin configuration 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 sda 13 14 12 11 vcc cput1/pii1 vref vin1 reset# vin2(+3.3vin) cput2/pii2 gnd fanfault#/gpo3 ovt# smi# pwmout2 scl pwmout1 batfault#/gpo4 fanin2/gpo2 fanin1/gpo1 vin3(vbat) pwr_dn#
w83l 784r preliminary publication release date: oct. 1999 - 8 - revision 0.55 5. pin description i/o 12t - ttl level bi - directional pin with 12 ma source - sink capability i/o 12ts - ttl level and schmitt trigger out 12 - output pin with 12 ma source - sink capability aout - output pin(analog) od 12 - open - drain output pin with 12 ma sink capability in t - ttl level input pin in ts - ttl level input pin and schmitt trigger ain - input pin(analog) pin name pin no. type description fanin1 / gpo1 1 i n ts / out 12 0v to +5v amplitude fan tachometer input. (default) / general purpose output . this multi - functional pin is programmable. fanin2 / gpo2 2 i n ts / out 12 0v to +5v amplitude fan tachometer input. (default) / general purpose output . this multi - functional pin is programmable. pwmout1 3 od 12 / out 12 fan sp eed control pwm output. this pin is default open - drain. it can be programmed as an output pin which can drive a high or a low. pwmout2 4 od 12 / out 12 fan speed control pwm output. this pin is default open - drain. it can be programmed as an output pin whic h can drive a high or a low. fanfault# / gpo3 5 od 12 active - low output. this pin will be a logic low when fan1 or fan2 is abnormally stopped. (default) / general purpose output . this multi - functional pin is programmable. pwr_dn# 6 in t power down i nput. when set this pin low, all output pins would be tristate except the pin15 reset# which will keep high. smi# 7 od 12 system management interrupt. ovt# 8 od 12 over temperature shutdown output. scl 9 in ts serial bus clock. sda 10 od 12 serial bus bi - directional data. batfault# / gpo4 11 od 12 active - low output. this pin will be a logic low when battery abnormally drops below the low limit or above the high limit. (default) / general purpose output . this multi - functional pin is programmable. gnd 12 ground ground.
w83l 784r preliminary publication release date: oct. 1999 - 9 - revision 0.55 pin discription, continued pin name pin no. type description vin3(vbat) 13 ain 0v to 4.096v fsr analog inputs. ( this pin should be connected to dc battery. if this voltage is above 4.096v, it should be reduced with the external resistors so that the input voltage will be under 4.096v. ) vin2(+3.3vin) 14 ain 0v to 4.096v fsr analog inputs. (this pin should be connected to 3vcc .) reset# 15 od 12 active - low reset output. reset# remains low while the 5vcc and +3.3v are below the reset threshold. it remains low for 200ms after the reset condition is terminated . vin1(vcore) 16 ain 0v to 4.096v fsr analog inputs. vref 17 aout reference voltage. cput2 / pii2 18 ai n thermistor terminal input.(default) / pentium tm ii diode input. this multi - functional pin is programmable. cput1 / pii1 19 ai n thermistor terminal input.(default) / pentium tm ii diode input. this multi - functional pin is programmable. vcc 20 power +5vcc power supply input.
w83l 784r preliminary publication release date: oct. 1999 - 10 - revision 0.55 6. functional descripti on 6.1 general description the W83L784R provides at most 4 analog positive inputs, 2 fan speed monitors, 2 sets for fan pwm (pulse width modulation) smart fan control , 2 remote thermal inputs from remote thermistors or 2n3904 transistors or pentium tm ii (des chutes) thermal diode outputs and one on - chip thermal detection. W83L784R also provides the power good (reset) output for 3v and 5v power detection and two fault output pins issuing hardware warning if battery and fans become abnormal. when start the mon itor function on the chip, the watch dog machine monitor every function and store the value to registers. if the monitor value exceeds the limit value, the interrupt status will be set to 1. 6.2 access interface the W83L784R provides i 2 c serial bus to read/w rite internal reigsters. in the W83L784R there are three serial bus address. the first address defined at cr[4ah] can read/write all registers excluding cput1/cput2 temperature sensor registers and its address default value is 0101101. the address for cpu t1 defined at cr[4bh] bit2 - 0 only read/write cput1 temperature sensor registers and the address default value is 1001001. the address for cput2 defined at cr[4bh] bit2 - 0 only read/write cput1 temperature sensor registers and the address default value is 10 01000. 6.2.1 the first serial bus access timing are shown as follow: (a) serial bus write to internal address register followed by the data byte 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by 784r r/w ack by 784r scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by 784r stop by master scl sda (continued) 7 8 0 7 8 0 7 8 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte figure 1. serial bus write to internal address register followed by the data byte
w83l 784r preliminary publication release date: oct. 1999 - 11 - revision 0.55 (b) serial bus write to internal address register only 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by 784r r/w ack by 784r scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 2. serial bus write to internal address register only stop by master (c) serial bus read from a register with the internal address register prefer to desired location 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by 784r scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte figure 3. serial bus read from internal address register stop by master 6.2.2 the serial bus timing of the temperature cput1 and cput2 is shown as follow: (a) typical 2 - byte read from preset pointer location (temp, t os , t hys t ) 0 start by master 0 1 0 1 1 0 1 d7 d1 d0 ack by master r/w ack by 784r scl sda 7 8 0 7 8 frame 2 msb data byte frame 1 serial bus address byte figure 4. typical 2-byte read from preset pointer location d7 d1 d0 0 7 stop by master ... ... ... no ack by master ... frame 3 lsb data byte
w83l 784r preliminary publication release date: oct. 1999 - 12 - revision 0.55 (b) typical pointer set followed by immediate read for 2 - byte register (temp, t os , t hyst ) 0 start by master d7 d1 d0 ack by master ack by 784r scl sda 7 8 0 7 8 0 frame 4 msb data byte frame 3 serial bus address byte figure 5. typical pointer set followed by immediate read for 2-byte register d7 d1 d0 0 7 stop by master ... ... ... no ack by master ... frame 5 lsb data byte 0 start by master 1 0 0 1 a2 a1 a0 r/w ack by 784r scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by 784r frame 2 pointer byte 1 0 0 1 a2 a1 a0 r/w 0 0 0 0 0 0 (c) typical read 1 - byte from configuration register with preset pointer 0 start by master d7 d2 ack by 782d scl sda 7 8 0 frame 2 data byte frame 1 serial bus address byte figure 6. typical 1-byte read from configuration with preset pointer d0 7 stop by master no ack by master 1 0 0 1 a2 a1 a0 r/w d1 d5 d4 d3 d6 8
w83l 784r preliminary publication release date: oct. 1999 - 13 - revision 0.55 (d) typical pointer set fo llowed by immediate read from configuration register 0 repea start by master d7 d5 d4 ack by 784r scl (cont..) sda (cont..) 7 8 0 frame 4 msb data byte frame 3 serial bus address byte figure 7. typical pointor set followed by immediate read from temp 2/3 configuration register d2 d1 d0 7 stop by master no ack by master 0 start by master 1 0 0 1 a2 a1 a0 r/w ack by 784r scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by 784r frame 2 pointer byte 1 0 0 1 a2 a1 a0 r/w ... ... d6 d3 8 7 8 0 0 0 0 0 0 (e) temperature configuration register write 0 ack by 784r scl (cont...) sda (cont...) 7 8 frame 3 configuration data byte figure 8. configuration register write 0 start by master 1 0 0 1 a2 a1 a0 r/w ack by 784r scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by 784r frame 2 pointer byte 0 0 d4 d3 d2 d1 0 d0 stop by master 0 0 0 0 0 0 0 7 8
w83l 784r preliminary publication release date: oct. 1999 - 14 - revision 0.55 (f) temperature t os and t hyst write 0 ack by 784r scl (cont...) sda (cont...) 7 8 frame 3 msb data byte figure 9. configuration register write 0 start by master 1 0 0 1 a2 a1 a0 r/w ack by 784r scl sda 7 8 0 frame 1 serial bus address byte 4 d1 d0 ack by 784r frame 2 pointer byte d6 d5 d4 d3 d2 d1 d7 d0 0 7 8 d6 d5 d4 d3 d2 d1 d7 d0 ack by 784r stop by master frame 4 lsb data byte 7 8 0 0 0 0 0 0
w83l 784r preliminary publication release date: oct. 1999 - 15 - revision 0.55 6.3 analog in puts the maximum input voltage of the analog pin is 4.096v because the 8 - bit adc has a 16mv lsb. really, the application of the pc monitoring would most often be connected to power suppliers. the cpu v - core voltage and +3.3v voltage can directly connected to these analog inputs. the 5vsb and battery inputs should be reduced a factor with external resistors so as to obtain the input range. as figure 10 shows. vin1(vcore) vin2(+3.3v) vin3(vbat) pin 14 pin 13 pin 20 vcc r1 10v(battery dc) 8-bit adc with 16mv lsb typical thermister connection 232k, 1% r thm pin 17 cput pin 19 positive inputs 10k, 25 c **the connections of cput2 is same as cput1 r2 r pin 16 vref 10k, 1% 99k, 1% figure. 10. 6.3.1 monitor over 4.096v voltage: the input voltage vi n3 can be expressed as following equation. vin v r r r bat dc 3 2 1 2 = + - the value of r1 and r2 can be selected to 232k ohms and 99k ohms, respectively, when the input voltage v bat - dc is 10v. the node voltage of vin3 can be subject to less than 4.096v for the maxim un input range of the 8 - bit adc. the pin 24 is connected to the power supply vcc with +5v. there are two functions in this pin with 5v. the first function is to supply internal analog power in the W83L784R and the second function is that this voltage with 5v is connected to internal serial resistors to monitor the +5v voltage. the value of two serial resistors are 34k ohms and 50k ohms so that input voltage to adc is 2.98v which is less than 4.096v of adc maximum input voltage. the express equation can rep resent as follows.
w83l 784r preliminary publication release date: oct. 1999 - 16 - revision 0.55 v vcc k k k v in = + @ 50 50 34 2 98 w w w . where vcc is set to 5v. 6.3.2 power good for 3v and 5v on power up, once vcc(5v) reaches 1v, reset# will be a logic low. as 3v and vcc(5v) rise, reset# remains asserted. if 3v and vcc(5v) both exceed the rese t threshold, reset becomes a logic high after a time equal to the reset pulse width (trst, typically 200ms).(figure 11). if a power fail or a brownout happens(i.e. 3v or vcc(5v) drops below the threshold), reset# output is asserted. as long as the 3v and vcc(5v) remain below the reset threshold, reset# output remains asserted. therefore, a brownout condition that interrupts a previously initiated reset pulse causes an additional 200ms delay from the time the latest interruption occurred. on power - on, on ce 3vor vcc(5v) drops below the reset threshold, reset# are guaranteed to be asserted for vcc 3 1v. 0 1 2 3 reset 0 5 4 5 v rs t trst v rs t vcc 0 1 2 3 4 v rs t v rs t 3.3v 0 1 2 3 reset 0 5 4 5 v rst trst v rst trst v rst vcc the time of voltage over 4v is less than trst figure 11
w83l 784r preliminary publication release date: oct. 1999 - 17 - revision 0.55 6.3.3 battery fault alarm W83L784R provides a good protection for dc battery. set vin3 to monitor dc battery voltage and ena ble vbat fault function. when vin3(pin13) voltage exceeds high or low limit value, pin batfault# will be asserted. 6.4 temperature measurement machine the temperature data format is 8 - bit two? - complement for internal sensor and 9 - bit two - complement for sen sor cput1 and cput2. the 8 - bit temperature data can be obtained by reading the cr[27h]. the 9 - bit temperature data (cput1 and cput2) can be obtained by reading cr[00h] of its serial bus address. the format of the temperature data is show in table 1. temp erature 8 - bit digital output 9 - bit digital output 8 - bit binary 8 - bit hex 9 - bit binary 9 - bit hex +125 c 0111,1101 7dh 0,1111,1010 0fah +25 c 0001,1001 19h 0,0011,0010 032h +1 c 0000,0001 01h 0,0000,0010 002h +0.5 c - - 0,0000,0001 001h +0 c 0000,0000 00h 0,0000,0000 000h - 0.5 c - - 1,1111,1111 1ffh - 1 c 1111,1111 ffh 1,1111,1110 1ffh - 25 c 1110,0111 e7h 1,1100,1110 1ceh - 55 c 1100,1001 c9h 1,1001,0010 192h table 1. 6.4.1 monitor temperature from thermistor: the W83L784R can connect three thermistors t o measure three different envirment temperature. the specification of thermistor should be considered to (1) b value is 3435k, (2) resistor value is 10k ohms at 25 c. in the figure 10, the themistor is connected by a serial resistor with 10k ohms, then con nect to vref (pin 17). 6.4.2 monitor temperature from pentium ii tm thermal diode or bipolar transistor 2n3904 the W83L784R can alternate the thermistor to pentium ii tm (deschutes) thermal diode interface or transistor 2n3904 and the circuit connection is shown as figure 12. the pin of pentium ii tm d - is
w83l 784r preliminary publication release date: oct. 1999 - 18 - revision 0.55 connected to power supply ground (gnd) and the pin d+ is connected to pin piix in the W83L784R. the resistor r=30k ohms should be connected to vref to supply the diode bias current and the bypass capacitor c=3300 pf should be added to filter the high frequency noise. the transistor 2n3904 should be connected to a form with a diode, that is, the base (b) and collector (c) in the 2n3904 should be tied togeter to act as a thermal diode. 2n3904 c e b r=30k, 1% c=3300pf bipolar transistor temperature sensor pentium ii cpu d+ d- therminal diode c=3300pf r=30k, 1% vref piitdx piitdx or W83L784R figure 12. 6.4.3 ov er temperature W83L784R provides two external thermal sensors to detect temperature. when detected temperature exceeds the over - temperature value, pin ovt# will be asserted until the temperature goes below the hysteresis temperature. pin ovt# has 3 opera ting modes: 6.4.3.1 acpi mode : at this mode, temperature exceeding one level of temperature sepeartion , starting from 0 degree, causes the ovt# output activated. ovt# will be activated again once temperature exceeding the next level. ovt# output will act the sa me manner when temperature goes down. (figure 13). the granularity of temperature separation between each ovt# output signal can be programmed at bank0 cr[4fh]. the piority of this mode is higher than comparator mode and interrupt mode .
w83l 784r preliminary publication release date: oct. 1999 - 19 - revision 0.55 0 10 20 30 40 50 100 90 80 70 60 ovt# ('c) current temperature figure 13. 6.4.3.2 comparator mode : at this mode, temperature exceeding t o causes the ovt# output activated until the temperature is less than t hyst . ( figure 14) 6.4.3.3 interrupt mode: at this mode, temperature exceeding t o causes the ovt# output activated indefinite ly until reset by reading cput1 or cput2 registers. temperature exceeding t o , then ovt# asserted, and then temperature going below t hyst will also cause the ovt# activated indefinitely until reset by reading temperature sensor2 or sensor 3 registers. once the ovt# is activated by exceeding t o , then reset, if the temperature remains above t hyst , the ovt# will not be activated again.( figure 14) t hyst * * * *interrupt reset when cput1/cput2 is read ovt# ovt# * (comparator mode; default) (interrupt mode) to figure 14.
w83l 784r preliminary publication release date: oct. 1999 - 20 - revision 0.55 6.5 fan speed count and fan speed control 6.5.1 fan speed count inputs are provides for signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage can not be over +5.5v. if the input signals from the tachometer outputs are over the vcc, the external trimming circuit sh ould be added to reduce the voltage to obtain the input specification. the normal circuit and trimming circuits are shown as figure 15. determine the fan counter according to: count rpm divisor = 1 35 10 6 . in other words, the fan speed counter has been read from r egister cr28 or cr29 or cr2a, the fan speed can be evaluated by the following equation. rpm count divisor = 1 35 10 6 . the default divisor is 2 and defined at cr49.bit0~2, bit4~6 which are three bits for divisor. that provides very low speed fan counter such as pow er supply fan. the followed table is an example for the relation of divisor, prm, and count. divisor nominal prm time per revolution counts 70% rpm time for 70% 1 8800 6.82 ms 153 6160 9.74 ms 2 (default) 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms 128 68 872.64 ms 153 48 1246.72 ms table 2.
w83l 784r preliminary publication release date: oct. 1999 - 21 - revision 0.55 fan connector fan out +5v gnd pull-up resister 4.7k ohms +5v +5v fan input pin 1 / 2 w83l784 r fan connector fan out +5v gnd pull-up resister 4.7k ohms +5v fan input pin 1 / 2 W83L784R 2k 10k figure 15-2. fan with tach pull-up to +5v, or totem-pole output and register attenuator figure 15-1. fan with tach pull-up to +5v fan connector fan out +5v gnd pull-up resister > 1k +5v fan input pin 1 / 2 w83l784 r fan connector fan out +5v gnd pull-up resister < 1k or totem-pole output +5v fan input pin 1 / 2 W83L784R > 1k figure 15-4. fan with tach pull-up to +5v, or totem-pole putput and zener clamp figure 15-3. fan with tach pull-up to +5v and zener clamp 3.9v zener 3.9v zener diode diode diode diode 6.5.2 fan speed control the w83l 784r provides four sets for fan pwm speed control. the duty cycle of pwm can be programmed by a 8 - bit register which are defined in the bank0 cr81h and cr83h. the default duty cycle is set to 100%, that is, the default 8 - bit registers is set to ffh. the e xpression of duty can be represented as follows. duty cycle programmed 8 - bit regist er value 255 - = (%) 100%
w83l 784r preliminary publication release date: oct. 1999 - 22 - revision 0.55 +5v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g figure 16. 6.5.3 smart fan control smart fan control provides two mechanisms. one is thermal cruise mode and the other is fan speed cruise mode. 6.5.3.1 thermal cruise mode at thi s mode, W83L784R provides the smart fan system which can control the fan speed automatically depend on current temperature to keep it with in a specific range. at first a wanted temperature and interval must be set (ex. 55 c 3 c) by bios, as long as th e current temperature remains below the setting value, the fan will be off. once the temperature exceeds the setting high limit temperature ( 58 c), the fan will be turned on with a specific speed set by bios (ex: 80% duty cycle) and automatically controll ed its pwm duty cycle with the temperature varying. three conditions may occur : (1) if the temperature still exceeds the high limit (ex: 58 c), pwm duty cycle will increase slowly. if the fan has been operating in its fully speed but the temperature stil l exceeds the high limit(ex: 58 c), a warning message or a fan_fault signal(pin5) will be issued to protect the system. (2) if the temperature goes below the high limit (ex: 58 c), but above the low limit (ex: 52 c), the fan speed will be fixed at the cur rent speed because the temperature is in the target area(ex: 52 c ~ 58 c). (3) if the temperature goes below the low limit (ex: 52 c), pwm duty cycle will decrease slowly to 0 or a preset value until the temperature exceeds the low limit. figure 17 gives an illustration for thermal cruise mode .
w83l 784r preliminary publication release date: oct. 1999 - 23 - revision 0.55 55`c 58`c 52`c pwm duty cycle 100 0 50 fan start = 20% a b c d figure 17 - 1. 55`c 58`c 52`c pwm duty cycle 100 0 50 fan start = 20% fan stop = 10% fan start = 20% a b c d figure 17 - 2. 6.5.3.2 fan speed cruise mode at this mode, W83L784R provides the smart fan system which can control the fan speed automatically depend on current fan spes ed to keep it with in a specific range. a wanted fan speed count and interval must be set (ex. 160 10 ) by bios. as long as the fan speed count is the specific range, pwm duty will keep the current value. if current fan speed count is higher than the hi gh limit (ex. 160+10), pwm duty will be increased to keep the count less than the high limit. otherwise, if current fan speed is less than the low limit(ex. 160 - 10), pwm duty will be decreased to keep the count higher than the low limit. see figure 18 exam ple.
w83l 784r preliminary publication release date: oct. 1999 - 24 - revision 0.55 160 170 150 pwm duty cycle 100 0 50 a c count figure 18. of cource, smart fan control system can be disabled and the fan speed control algorithem can be progrmmed by bios or application software. 6.5.4 fan fault alarm W83L784R can monitor fan speed by detecting fan speed counter val ue. when fan speed count is higher than high limit count value(cr58h) or is less than low limit count value(cr59h), pin fanfault# is asserted. 6.6 smi# 6.6.1 temperature pin smi# for temperature has 3 modes. 6.6.1.1 comparator interrupt mode temperature exceeding t o causes an interrupt and this interrupt will be reset by reading all the interrupt status registers. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will occur again when the nex t conversion has completed. if an interrupt event has occurred by exceeding t o and not reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t hyst . ( figure 19 - 1 ) 6.6.1.2 two - times int errupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt status register. once an interrupt event has occurred by exc eeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 19 - 2 )
w83l 784r preliminary publication release date: oct. 1999 - 25 - revision 0.55 6.6.1.3 one - time interrupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will not cause an interrupt. once an interrupt event has occurred by exceeding t o , then going below t hyst, an interrupt will not occur again until the temperature exceeding t o . (figure 19 - 3 ) t oi t hyst * * * figure 19-1. comparator interrupt mode *interrupt reset when interrupt status registers are read t oi t hyst figure 19-2. two-times interrupt mode smi# smi# * * * * * *interrupt reset when interrupt status registers are read t oi t hyst figure 19-3. one-time interrupt mode smi# * *
w83l 784r preliminary publication release date: oct. 1999 - 26 - revision 0.55 6.6.2 voltage smi# inte rrupt for voltage is two - times interrupt mode. voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt status register. (figure 20 - 1 ) 6.6.3 fan smi# interrupt for fan is two - times interrupt mode. fan count exceeding the limit, or exceeding and then going below the limit( set at value ram index 3bh and 3ch) , will causes an interrupt if the previous interrupt has been reset by reading all the interrupt status register. ( figure 20 - 2 ) * * * figure 20-1. voltage smi# mode *interrupt reset when interrupt status registers are read figure 20-2. fan smi# mode smi# * high limit low limit * smi# * fan count limit
w83l 784r preliminary publication release date: oct. 1999 - 27 - revision 0.55 7. registers and ram 7.1 configuration register -- index 40h power on default [7:0] = 0000,0001 b bit name read/write description 7 initialization read/write a one restores power on default value to all registe rs except the serial bus address register. this bit clears itself since the power on default is zero. 6 - 4 reserved read/write reserved 3 dis_pwrok read/write disable power ok function . if this bit set to 1, the pwr_dn# (pin 6) will keep logical high no m ater what the pwoer vdd or +3.3v drop to the threshold voltage (4.0v and 2.6v, respectively). 2 reserved reserved reserved 1 int_ clear read/write a one disables the smi# outputs without affecting the contents of interrupt status registers. the device wi ll stop monitoring. it will resume upon clearing of this bit. 0 start read/write a one enables startup of monitoring operations, a zero puts the part in standby mode. note: the outputs of interrupt pins will not be cleared if the user writes a zero to t his location after an interrupt has occurred unlike "int_clear'' bit. 7.2 interrupt status register 1 -- index 41h power on default [7:0] = 0000,0000 b bit name read/write description 7 temp3 read only a one indicates a high or low limit has been exceeded f rom cput2 sensor. 6 temp2 read only a one indicates a high or low limit has been exceeded from cput1 sensor. 5 temp1 read only a one indicates a high or low limit has been exceeded from W83L784R internal temperature sensor. 4 reserved reserved reserved 3 vccin read only a one indicates a high or low limit has been exceeded. ( vcc, +5v) 2 3vin read only a one indicates a high or low limit has been exceeded. (vin2) 1 vbatin read only a one indicates a high or low limit has been exceeded.(vin3
w83l 784r preliminary publication release date: oct. 1999 - 28 - revision 0.55 ) 0 vcoi n read only a one indicates a high or low limit has been exceeded. (vin1) 7.3 interrupt status register 2 -- index 42h power on default [7:0] = 0000,0000 b bit name read/write description 7 - 4 reserved read only read 0. 3 tar_t2 read only cput2 target status . a one indicate cput2 temperature with fan 2 full speed can not be in the specific range after 3 minutes. 2 tar_t1 read only cput1 target status. a one indicate cput1 temperature with fan 1 full speed can not be in the specific range after 3 minutes. 1 fan2 read only a one indicates the fan count limit has been exceeded. 0 fan1 read only a one indicates the fan count limit has been exceeded. 7.4 smi mask register 1 -- index 43h power on default <7:0> = 0000,0000 b bit name read/write description 7 msk_t 3_smi read/write a one disables the corresponding interrupt status bit for smi interrupt.(cput2 target temperature) 6 msk_t2_smi read/write a one disables the corresponding interrupt status bit for smi interrupt.(cput1 ta rget temperature) 5 msk_t1_smi read/write a one disables the corresponding interrupt status bit for smi interrupt. (internal thermal diode) 4 reserved reserved reserved 3 msk_vcc_smi read/write a one disables the corresponding interrupt status bit for smi interrupt. (vcc, +5v) 2 msk_3v_smi read/write a one disables the corresponding interrupt status bit for smi interrupt. (pin vin2) 1 msk_vbat_s mi read/write a one disables the corresponding interrupt s tatus bit for smi interrupt.(pin vin3)
w83l 784r preliminary publication release date: oct. 1999 - 29 - revision 0.55 interrupt.(pin vin3) 0 msk_vco_smi read/write a one disables the corresponding interrupt status bit for smi interrupt. (pin vin1) 7.5 smi y mask register 2 -- index 44h power on default [7:0] = 0000,0000 b bit name read/write description 7 - 4 reserved read/write reserved. 3 msk_tar2_smi read/write a one disables the corresponding interrupt status bit for smi interrupt. (cput2 target temperature ) 2 msk_tar1_smi read/write a one disables the corresponding interrupt status bit for smi interrupt. (cput1 target temperature ) 1 msk_fan2_smi read/write a one disables the corresponding interrupt status bit for smi interrupt. (fan 2 speed counter) 0 msk_fan1_s mi read/write a one disables the corresponding interrupt status bit for smi interrupt. (fan 1 speed counter) 7.6 real time hardware status register i -- index 45h power on - [7:0] = 0000,0000 b bit name read/write description 7 temp3_sts re ad only temperature sensor 3 (cpu t2) status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. 6 temp2_sts read only temperature sensor 2 (cpu t1) status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. 5 temp1_sts read only temperature sensor 1 (internal thermal diode) status. set 1, the voltage of temperature sensor is over the limit value. se t 0, the voltage of temperature sensor is in the limit range. 4 reserved reserved reserved. 3 vccin_sts read only +5v voltage status. set 1, the voltage of +5v is over the limit value. set 0, the voltage of +5v is in the limit range.
w83l 784r preliminary publication release date: oct. 1999 - 30 - revision 0.55 2 3v_sts read only +3.3v voltage status. set 1, the voltage of +3.3v is over the limit value. set 0, the voltage of +3.3v is in the limit range. 1 vbat_sts read only vbat (vin3) voltage status. set 1, the voltage of vbat(vin3) is over the limit value. set 0, the voltage o f vbat(vin3) is in the limit range. 0 vco_sts read only vcore a voltage status. set 1, the voltage of vcore a is over the limit value. set 0, the voltage of vcore a is in the limit range. 7.7 real time hardware status register ii -- index 46h power on defa ult [7:0] = 0000 - 0000 b bit name read/write description 7 - 4 reserved read only read 0. 3 tart2_sts read only cput2 target status. set 1, when cput2 target temperature with fan 2 full speed can not be in the range after 3 minutes. set 0, the temperature or speed is in the specific range . 2 tart1_sts read only cput1 targert status. set 1, when cput1 target temperature with fan 1 full speed can not be in the range after 3 minutes. set 0, the temperature or speed is in the specific range .. 1 fan2_sts rea d only fan 2 status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is in the limit range. 0 fan1_sts read only fan 1 status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is in the limit range. 7.8 reserved register -- index 47h - 48h reserved. 7.9 fan divisor register -- index 49h power on default [7:4] = 0001,0001 b bit name read/write description 7 reserved read/write reserved. 6 - 4 f2_sp_crtl[2:0] read/write fan2 speed control.
w83l 784r preliminary publication release date: oct. 1999 - 31 - revision 0.55 000 - divide by 1; 001 - divide by 2; 010 - divide by 4; 011 - divide by 8. 100 - divide by 16. 101 - divide by 32. 110 - divide by 64. 111 - divide by 128. 3 reserved read/write reserved. 2 - 0 f1_sp_ctrl[2:0] read/write fan1 speed control. 000 - divide by 1 ; 001 - divide by 2; 010 - divide by 4; 011 - divide by 8. 100 - divide by 16. 101 - divide by 32. 110 - divide by 64. 111 - divide by 128. 7.10 serial bus address (for voltage ,fan, and internal temperature ) register -- address 4ah power on default [7:0] = 0010,1101 b bit name read/write description 7 reserved read only 6 - 0 serial bus address read/write serial bus address [6:0]. 7.11 cput1 temperature and cput2 temperature serial bus address register -- index 4bh power on default [7:0] = 0000,0001 b bit na me read/write description 7 dis_cput2 read/write disable cput2 temperature function. set to 1, disable temperature 3 sensor and can not access any data from temperature sensor 3. note that the relative
w83l 784r preliminary publication release date: oct. 1999 - 32 - revision 0.55 functions of status, and smi# will be disable. 6 - 4 i 2caddr3[2:0] read/write temperature 3 seiral bus address. the serial bus address is 1001xxx. where xxx are defined in these bits. 3 dis_cput1 read/write disable cput1 temperature function. set to 1, disable temperature sensor and can not access any data f rom temperature sensor 2. note that the relative functions of status, and smi# will be disable. 2 - 0 i2caddr2[2:0] read/write temperature 2 serial bus address. the serial bus address is 1001xxx. where xxx are defined in these bits. 7.12 winbond vendor id (low byte) - index 4ch (auto increase) power - on default [7:0] = 1010,0011 b (a3h) bit name read/write description 7:0 vidl[7:0] read only vendor id low byte. default a3h. 7.13 winbond vendor id (high byte) - index 4dh (no auto increase) power - on default [7:0] = 0 101,1100 b (5ch) bit name read/write description 7:0 vidh[7:0] read only vendor id high byte. default 5ch 7.14 chip id -- index 4eh power on default [7:0] = 0101,0000 b bit name read/write description 7 - 0 chipid[7:0] read only winbond chip id number. read this register will return 50h for W83L784R. 7.15 acpi temperature increment register -- index 4fh power on deafult [7:0] = 0000,0101 b bit name read/write description 7 reserved read/write reserved. 6 - 0 diffreg[6:0] readwrite acpi temperature increment regis ter. if set to this register to non - zero value, the ovt# signal will be actived at pointer of the temperaure of times of
w83l 784r preliminary publication release date: oct. 1999 - 33 - revision 0.55 diffreg (i.e. diffreg*n, where n is non - zero integer). the default value is 5 degree c. 7.16 ovt# property select -- index 50h power on de fault [7:0] = 0000,0000 b bit name read/write description 7 - 6 reserved read/write reserved. 5 - 4 ovt_md[1:0] read/write ovt# mode select. there are three ovt# signal output type. <00> - comparator mode: (default) temperature exceeding t o causes the ovt# o utput activated until the temperature is less than t hyst . <01> - interrupt mode: setting temperature exceeding t o causes the ovt# output activated indefinitely until reset reading temperature sensor 1/2/3 registers. temperature exceeding t o , then ovt# res et, and then temperature going below t hyst will also cause the ovt# activated indifinitely until reset by reading temperature sensor 1/2/3. onece the ovt# will not be activated by exceeding t o , then reset, if the temperature remains above t hyst , the ovt# w ill not be actived agian. <10> - acpi mode: if set to 1 then enable acpi ovt# output. which is always send an ovt# signal when the temperature over the acpi temperature increment value defined at index 4fh. 3 en_ovt3 read/write enable cput2 temperature se nsor over - temperature (ovt) output if set to 1. default 0, disable cput2 ovt output through pin ovt#. the pin ovt# is wire or with ovt1 and ovt2. 2 en_ovt2 read/write enable cput1 temperature sensor over - temperature (ovt) output if set to 1. default 0, disable cput1 ovt output through pin ovt#. the pin ovt# is wire or with ovt1 and ovt3. 1 en_ovt1 read/write enable internal temperature sensor over - temperature (ovt) output if set to 1. default 0, disable ovt1 output through pin ovt#. the pin ovt# is wire or with ovt2 and ovt3. 0 ovtpol read/write over - temperature polarity. write 1, ovt# active high. write 0, ovt# active low. default 0.
w83l 784r preliminary publication release date: oct. 1999 - 34 - revision 0.55 write 0, ovt# active low. default 0. 7.17 smi# property select -- index 51h power on - <7:0> -- 0000,0100 b bit name read/write description 7 - 4 reserved read/wri te reserved. 3 - 2 temp_smi_md[1:0] read/write temperature smi mode select. <00> - comparator interrupt mode: temperature 1/2/3 exceeds t o (over - temperature) limit causes and interrupt and this interrupt will be reset by reading all the interrupt stauts. < 01> - two time interrupt mode: (default) this bit use in temperature sensor 1/2/3 interrupt mode with hysteresis type. temperature exceeding t o , causes an interrupt and then temperature going below t hyst will also cause an interrupt if the previous interrup t has been reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst . <10> - one time interrupt mode: this bit use in temperature sensor 1/2/3 interrupt mode with hysteresis type. temperature exceeding t o (over - temperature, defined in bank 1/2) causes an interrupt and then temperature going below t hyst (hysteresis temperature, defined in bank 1/2) will not cause an interrupt. once an interrupt event has oc curred by exceeding t o , then going below t hyst , and interrupt will not occur again until the temperature exceeding t o . 1 en_smi# read/write enable smi# output. a one enables the smi# interrupt output. 0 smipol read/write smi# polarity. write 1, smi# act ive high. write 0, smi# active low. default 0. 7.18 fanin1/gpo1, fanin2/gpo2 and beep/gpo3 control register - indxe 52h power on default [7:0] = 0000,0000 b bit name read/write description 7 gpo4_val read/write gpo4 output value. gpo4 output value if en_gpo4 is set to 1. write 1, then pin 11 (gpo4) always generate logic
w83l 784r preliminary publication release date: oct. 1999 - 35 - revision 0.55 high signal. write 0, pin 11 (gpo4) always generates logic low signal. this bit default 0. 6 en_gpo4 read/wite enable gpo4 function. set to 0 (default), pin 11 (batfault#/gpo3) acts as batfaul t# whcih is battery voltage out of the limit value. set to 1, this pin 11 acts as gpo4 control function and the output value of gpo4 is programmed by this register bit 7. 5 gpo3_val read/write gpo3 output value. gpo3 output value if en_gpo3 is set to 1. w rite 1, then pin 5 (gpo3) always generate logic high signal. write 0, pin 5 (gpo3) always generates logic low signal. this bit default 0. 4 en_gpo3 read/wite enable gpo3 function. set to 0 (default), pin 5 (fanfault#/gpo3) acts as fan_fault whcih is fan c ount out of the limit value. set to 1, this pin 5 acts as gpo3 control function and the output value of gpo3 is programmed by this register bit 5. 3 gpo2_val read/write gpo2 output value. gpo2 output value if en_gpo2 is set to 1. write 1, then pin 2 (gpo2 ) always generate logic high signal. write 0, pin 2 (gpo2) always generates logic low signal. this bit default 0. 2 en_gpo2 read/write enable gpo2 function. which enable multiple function pin 2, named fanin2/gpo2, gpo2 function. set to 0 (default), pin 2 (fanin2/gpo2) acts as fanin2 whcih is fan clock input. set to 1, this pin 2 acts as gpo2 control function and the output value of gpo2 is programmed by this register bit 3. this output pin gpo2 can connect to power pmos gate to control fan on/off. 1 gpo1_ val read/write gpo1 output value. gpo1 output value if en_gpo1 is set to 1. write 1, then pin 1 (gpo1) always generate logic high signal. write 0, pin 1 (gpo1) always generates logic low signal. this bit default 0. 0 en_gpo1 read/write enable gpo1 functio n. which enable multiple function pin 1, named fanin1/gpo1, gpo1 function. set to 0 (default), pin 1 (fanin1/gpo1) acts as fanin1 whcih is fan clock input. set to 1, this pin 1 acts as gpo1 control function and the output value of gpo1 is programmed by thi s register bit 1. this output pin gpo2 can connect to power pmos gate to control fan on/off.
w83l 784r preliminary publication release date: oct. 1999 - 36 - revision 0.55 7.19 cput1/cput2 thermal sensor type register -- index 53h power on default [7:0] = 0000 - 0000 b bit name read/write description 7 - 4 reserved read/write reserved. 3 - 2 t3_type[1:0] read/write temperature sensor 3 (cpu t2) type. 0x - thermistor (10k @ 25 degree c, b=3435). 10 - 2n3904 transistor. 11 - intel thermal diode. 1 - 0 t2_type[1:0] read/write temperature sensor 2 (cpu t1) type. 0x - thermistor (10k @ 25 degree c, b=3435) 10 - 2n3904 transistor 11 - intel thermal diode. 7.20 misc control register -- index 54h power on default [7:0] = 0000 - 0000 b bit name read/write description 7 - 6 reserved read/write reserved. 5 pwm2_lm_enable read/write set 1, pwmout2 duty cycle will decrease to cr[89h] when temperature goes below target range. set 0, pwmout2 duty cycle will decrease to 0 when temperature goew below target range. 4 pwm1_lm_enable read/write set 1, pwmout1 duty cycle will decrease to cr[88h] when temperature goe s below target range. set 0, pwmout1 duty cycle will decrease to 0 when temperature goew below target range. 3 reserved reserved reserved 2 swp_fan2_pwm read/write swap cput2 pwm to internal temperature sensor pwm control. write this bit set to 1, fan2 pwm pwm control will refer to internal temperature senesor. 1 reserved reserved reserved 0 en_vbat_mnt readwrite write 1, enable battery voltage monitor. write 0, disable battery voltage monitor. (vin4/vbat)
w83l 784r preliminary publication release date: oct. 1999 - 37 - revision 0.55 7.21 fan/vbat fault control register -- index 55 h power on default [7:0] = 0000 - 0000 b bit name read/write description 7 - 3 reserved read/write reserved. 2 en_fan2_fault read/write enable fan 2 fault function. when fan 2 is out of the fan fault limit value (defined index 58 and 59), the pin 5 will go to low level. this function is wire - or with fan 1 fault if fan 1 fualt function is enable. 1 en_fan1_fault read/write enable fan1 fault function. when fan 1 is out of the fan fault limit value (defined index 56 and 57), the pin 5 will go to low level. th is function is wire - or with fan 2 fault if fan 2 fualt function is enable. 0 en_vbat_fault readwrite enable vbat fault function . set to 1, enable battery fault function. set to 0, disable this function. when battery voltage is out of the fault limit value (defined at index 5a and 5b), the pin 11 (batfault#) will be asserted. 7.22 fan 1 fault high limit count -- index 56h power on default [7:0] = 1111 - 1111 b bit name read/write description 7 - 0 fan_hi_lm read/write fan high count limit value. 7.23 fan 2 fault low limit count -- index 57h power on default [7:0] = 0000 - 0000 b bit name read/write description 7 - 0 fan_low_lm read/write fan low count limit value. 7.24 fan 2 fault high limit count -- index 58h power on default [7:0] = 1111 - 1111 b bit name read/write descri ption 7 - 0 fan_hi_lm read/write fan high count limit value.
w83l 784r preliminary publication release date: oct. 1999 - 38 - revision 0.55 7.25 fan 1 fault low limit count -- index 59h power on default [7:0] = 0000 - 0000 b bit name read/write description 7 - 0 fan_low_lm read/write fan low count limit value. 7.26 vbat fault high limit value -- index 5ah power on default [7:0] = 1111 - 1111 b bit name read/write description 7 - 0 vbat_hi_lm read/write vbat high limit value. 7.27 vbat fault low limit value -- index 5bh power on default [7:0] = 0000 - 0000 b bit name read/write description 7 - 0 vbat_low _lm read/write vbat low limit value. 7.28 fan 1 pre - scale register -- index 80h power on default [7:0] = 0000 - 0001 b bit name read/write description 7 pwm_clk_sel1 read/write pwm input clock select. this bit select fan 1 input clock to pre - scale divider. 0: 1 mhz 1: 125 khz 6 - 0 pre_scale1[6:0] read/write fan 1 input clock pre - scale. the divider of input clock is the number defined by pre - scale. thus, writing 0 transfers the input clock directly to counter. the maximum divider is 128 (7fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : :
w83l 784r preliminary publication release date: oct. 1999 - 39 - revision 0.55 7.29 fan 1 duty cycle select register -- 81h ( bank 0 ) power on default [7:0] 1111,1111 b bit name read/write description 7 - 0 f1_dc[7:0] read/write fan 1 duty cycle. this 8 - bit register determi nes the number of input clock cycles, out of 256 - cycle period, during which the pwm output is high. during smart fan 1 control mode, read this register will return smart fan duty cycle. 00h: pwm output is always logical low. ffh: pwm output is always logic al high. xxh: pwm output logical high percentage is (xx/256*100%) during one cycle. 7.30 fan 2 pre - scale register -- index 82h power on default [7:0] = 0000,0001 b bit name read/write description 7 pwm_clk_sel2 read/write pwm 2 input clock select. this bit se lect fan 2 input clock to pre - scale divider. 0: 1 mhz 1: 125 khz 6 - 0 pre_scale2[6:0] read/write fan 2 input clock pre - scale. the divider of input clock is the number defined by pre - scale. thus, writing 0 transfers the input clock directly to counter. the maximum divider is 128 (7fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : : 7.31 fan2 duty cycle select register -- index 83h
w83l 784r preliminary publication release date: oct. 1999 - 40 - revision 0.55 power on default [7:0] = 1111,1111 b bit name read/write description 7 - 0 f2_dc[7:0] read /write fan 2 duty cycle. this 8 - bit register determines the number of input clock cycles, out of 256 - cycle period, during which the pwm output is high. during smart fan 2 control mode, read this register will return smart fan duty cycle. 00h: pwm output is always logical low. ffh: pwm output is always logical high. xxh: pwm output logical high percentage is xx/256*100% during one cycle. 7.32 fan configuration register -- index 84h power on default [7:0] = 0000,0000 b bit name read/write description 7 - 2 reserve d read/write reserved 5 - 4 fan2_mode read/write fan 2 pwm control mode. 00 - manual pwm control mode. (default) 01 - thermal cruise mode. 10 - fan speed cruise mode. 11 - reserved. 3 - 2 fan1_mode read/write fan 1 pwm control mode. 00 - manual pwm control m ode. (default) 01 - thermal cruise mode. 10 - fan speed cruise mode. 11 - reserved. 1 fan2_ob read/write enable fan 2 as output buffer. set to 1, fanpwm1 can drive logical high or logical low. default pin 4 (fanpwm) is open - drain. 0 fan1_ob read/write en able fan 1 as output buffer. set to 1, fanpwm1 can drive logical high or logical low. default pin 3 (fanpwm) is open - drain. 7.33 cput1 target temperature register/ fan 1 target speed register -- index 85h
w83l 784r preliminary publication release date: oct. 1999 - 41 - revision 0.55 power on default [7:0] = 0000,0000 b cput1 target temp erature register for thermal cruise mode. bit name read/write description 7 reserved read/write reserved. 6 - 0 temp_tar_t1[6:0 ] read/write cput1 target temperature. only for thermal cruise mode while cr84h bit3 - 2 is 01. fan 1 target speed register for fan speed cruise mode. bit name read/write description 7 - 0 spd_tar_fan1[7 :0] read/write fan 1 target speed control. only for fan speed cruise mode while cr84h bit3 - 2 is 10. 7.34 cput2 target temperature register/ fan 2 target speed register -- index 86h powe r on - [7:0] = 0000,0000 b cput2 target temperature register for thermal cruise mode. bit name read/write description 7 reserved read/write reserved. 6 - 0 temp_tar_t2[6:0 ] read/write cput1 target temperature. only for thermal cruise mode while cr84h bit5 - 4 is 01. fan 2 target speed register for fan speed cruise mode. bit name read/write description 7 - 0 spd_tar_fan2[7 :0] read/write fan 1 target speed control. only for fan speed cruise mode while cr84h bit5 - 4 is 10. 7.35 tolerance of target temperature or t arget speed register -- index 87h power on default [7:0] = 0001,0001 b tolerance of cput1/cput2 target temperature register. bit name read/write description 7 - 4 tol_t2[3:0] read/write tolerance of fan 2 target temperature. only for thermal cruise mode. 3 - 0 tol_t1[3:0] read/write tolerance of fan 1 target temperature. only for
w83l 784r preliminary publication release date: oct. 1999 - 42 - revision 0.55 thermal cruise mode. tolerance of fan 1/2 target speed register. bit name read/write description 7 - 4 tol_fs2[3:0] read/write tolerance of fan 2 target speed count. only for fan sp eed cruise mode. 3 - 0 tol_fs1[3:0] read/write tolerance of fan 1 target speed count. only for fan speed cruise mode. 7.36 fan 1 pwm stop duty cycle register -- index 88h power on default [7:0] = 0000,0001 b bit name read/write description 7 - 0 stop_dc1[7:0] r ead/write in thermal cruise mode, pwm duty will be 0 if it decreases to under this value. this register should be written a non - zero minimum pwm stop duty cycle. 7.37 fan 2 pwm stop duty cycle register -- 89h ( bank 0 ) power on default [7:0] = 0000,0001 b bit name read/write description 7 - 0 stop_dc2[7:0] read/write in thermal cruise mode, pwm duty will be 0 if it decreases to under this register value. this register should be written a non - zero minimum pwm stop duty cycle. 7.38 fan 1 start - up duty cycle register -- index 8ah power on default [7:0] = 0000,0001 b bit name read/write description 7 - 0 start_dc1[7:0] read/write in thermal cruise mode, pwm duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. this register should be written a fan start - up duty cycle. 7.39 fan 2 start - up duty cycle register -- index 8bh
w83l 784r preliminary publication release date: oct. 1999 - 43 - revision 0.55 power on default [7:0] = 0000,0001 b bit name read/write description 7 - 0 start_dc2[7:0] read/write in thermal cruise mode, pwm duty will increase from 0 to t his register value to provide a minimum duty cycle to turn on the fan. this register should be written a fan start - up duty cycle. 7.40 fan 1 stop time register -- indxe 8ch power on default [7:0] = 0011,1100 b bit name read/write description 7 - 0 stop_time1[ 7:0] read/write in thermal cruise mode, this register determines the time of which pwm duty is from stop duty cycle to 0 duty cycle. the unit of this register is 0.1 second. the default value is 6 seconds. 7.41 fan 2 stop time register -- index 8dh power on d efault [7:0] = 0011,1100 b bit name read/write description 7 - 0 stop_time2[7:0] read/write in thermal cruise mode, this register determines the time of which pwm duty is from stop duty cycle to 0 duty cycle. the unit of this register is 0.1 second. the def ault value is 6 seconds. 7.42 fan step down time register -- index 8eh power on defualt [7:0] = 0000,1010 b bit name read/write description 7 - 0 step_up_t[7:0] read/write the time interval, which is 0.1 second unit, to decrease pwm duty in smart fan control mode. 7.43 fan step up time register -- index 8fh
w83l 784r preliminary publication release date: oct. 1999 - 44 - revision 0.55 power on default [7:0] = 0000,1010 b bit name read/write description 7 - 0 step_down_t[7:0 ] read/write the time interval, which is 0.1 second unit, to increase pwm duty in smart fan control mode. 7.44 temperat ure sensor 1 (internal thermal diode) offset register -- index 90h power - on default [7:0] = 0000,0000 b bit name read/write description 7 - 6 reserved read/write reserved. 5 - 0 offset1[5:0] read/write temperature 1 base temperature. this value is added to m onitor value, resulting in the current temperature. 01,1111 => +31 degree c 01,1110 => +30 degree c : 00,0001 => +1 degree c 00,0000 => +0 degree c 11,1111 => - 1 degree c 11,1110 => - 2 degree c : 10,0000 => - 32 degree 7.45 temperature sensor 2 (cpu t1) offset register -- index 91h power - on default [7:0] = 0000,0000 b bit name read/write description 7 - 6 reserved read/write reserved. 5 - 0 offset1[5:0] read/write temperature 2 (cput1) base temperature. this value is added to monitor value, resulting in th e current temperature. 01,1111 => +31 degree c 01,1110 => +30 degree c : 00,0001 => +1 degree c 00,0000 => +0 degree c
w83l 784r preliminary publication release date: oct. 1999 - 45 - revision 0.55 11,1111 => - 1 degree c 11,1110 => - 2 degree c : 10,0000 => - 32 degree 7.46 temperature sensor 3 (cpu t2) offset register -- index 92h power - on default [7:0] = 0000,0000 b bit name read/write description 7 - 6 reserved read/write reserved. 5 - 0 offset3[5:0] read/write temperature 3 (cpu t2) base temperature. this value is added to monitor value, resulting in the current temperature. 01,111 1 => +31 degree c 01,1110 => +30 degree c : 00,0001 => +1 degree c 00,0000 => +0 degree c 11,1111 => - 1 degree c 11,1110 => - 2 degree c : 10,0000 => - 32 degree 8. value ram and limit value 8.1 value ram -- index 20h - 3fh or 60h - 7fh index a6 - a0 index a6 - a 0 description 20h 60h pin vin1 reading (vcore) 21h 61h pin vin3 reading (vbat) 22h 62h pin vin2 reading (+3.3v) 23h 63h pin vcc reading (vcc,+5v) 24h 64h reserved 25h 65h reserved 26h 66h reserved 27h 67h internal temperature reading
w83l 784r preliminary publication release date: oct. 1999 - 46 - revision 0.55 28h 68h fan1 reading note: this location stores the number of counts of the internal clock per revolution. 29h 69h fan2 reading note: this location stores the number of counts of the internal clock per revolution. 2ah 6ah reserved 2bh 6bh vin1(vcore) high limit 2c h 6ch vin1(vcore) low limit 2dh 6dh vin3 (vbat) high limit 2eh 6eh vin3 (vbat) low limit 2fh 6fh vin2 (+3.3v) high limit 30h 70h vin2 (+3.3v) low limit 31h 71h vcc high limit 32h 72h vcc low limit 33h 73h reserved 34h 74h reserved 35h 75h reserved 36h 76h reserved 37h 77h reserved 38h 78h reserved 39h 79h over temperature limit (high) of internal temperature 3ah 7ah temperature hysteresis limit (low) of internal temperature 3bh 7bh fan1 fan count limit 3ch 7ch fan2 fan count limit. 3dh 7d h reserved 3e - 3fh 7e - 7fh reserved
w83l 784r preliminary publication release date: oct. 1999 - 47 - revision 0.55 9. temperature sensor 2 (cpu t1) registers the address of i 2 c is defined in bank0.reg4b. 9.1 temperature sensor 2 temperature register -- index 00h read only bit name read/write description 15 - 7 temp2[8:0] read only tempera ture bit [8:0] of sensor 2. (0.5 degree c precision) 6 - 0 reserved read only read 0. 9.2 temperature sensor 2 configuration register -- index 01h power - on default [7:0] = 0000,0000 b bit name read/write description 7 - 5 reserved read read 0. 4 - 3 fault read/w rite number of faults to detect before setting ovt# output to avoid false tripping due to noise. 2 - 1 reserved read/write reserved. 0 reserved read/write reserved. 9.3 temperature sensor 2 hysteresis register -- index 02h power - on - <15:0> = 0100,1011,0000,0 000 b bit name read/write description 15 - 7 thyst2[8:0] read/write temperature hysteresis bit 8 - 0. the temperature default 75.0 degree c. 6:0 reserved read read 0. 9.4 temperature sensor 2 over - temperature register -- index 03h power - on - <15:0> = 0101,0000 ,0000,0000 b bit name read/write description 15 - 7 tovf2[8:0] read/write over - temperature bit 8 - 0. the temperature default 80.0 degree c. 6:0 reserved read read 0.
w83l 784r preliminary publication release date: oct. 1999 - 48 - revision 0.55 10. temperature sensor 3 (cpu t2) registers the address of i 2 c is defined in bank0.reg4b. 10.1 te mperature sensor 3 temperature register -- index 00h read only bit name read/write description 15 - 7 temp2[8:0] read only temperature bit [8:0] of sensor 2. (0.5 degree c precision). 6 - 0 reserved read only read 0. 10.2 temperature sensor 3 configuration regis ter -- index 01h power - on - [7:0] = 0000,0000 b bit name read/write description 7 - 5 reserved read read 0. 4 - 3 fault read/write number of faults to detect before setting ovt# output to avoid false tripping due to noise. 2 - 1 reserved read only read 0. 0 reserved read/write reserved 10.3 temperature sensor 3 hysteresis register -- index 02h power - on default [15:0] = 0100,1011,0000,0000 b bit name read/write description 15 - 7 thyst3[8:0] read/write temperature hysteresis bit 8 - 0. the temperature default 75.0 de gree c. 6 - 0 reserved read only read 0. 10.4 temperature sensor 3 over - temperature register -- index 03h power - on - [15:0] = 0101,0000,0000,0000 b bit name read/write description 15 - 7 tovf3[8:0] read/write over - temperature bit 8 - 0. the temperature default 80 .0 degree c. 6 - 0 reserved read only read 0.
w83l 784r preliminary publication release date: oct. 1999 - 49 - revision 0.55 11. specifications 11.1 absolute maximum ratings parameter rating unit power supply voltage - 0.5 to 7.0 v input voltage - 0.5 to v dd +0.5 v operating temperature 0 to +70 c storage temperature - 55 to +150 c note : exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 11.2 dc characteristics (ta = 0 c to 70 c, v dd = 5v 10%, v ss = 0v) parameter sym. min. typ. max. unit conditions i/o 12t - ttl level bi - directional pin with source - sink capability of 12 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma input high leakage i lih + 10 m a v in = v dd input low leakage i lil - 10 m a v in = 0v i/o 12ts - ttl level bi - directional pin with source - sink capability of 12 ma and schmitt - trigger level input input low threshold voltage v t - 0.5 0.8 1.1 v v dd = 5 v input high threshold voltage v t+ 1.6 2.0 2.4 v v dd = 5 v hysteresis v th 0.5 1.2 v v dd = 5 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0v
w83l 784r preliminary publication release date: oct. 1999 - 50 - revision 0.55 11.2 dc char acteristics, continued parameter sym. min. typ. max. unit conditions out 12t - ttl level output pin with source - sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma od 8 - open - drain output pin with sink capability of 8 ma output low voltage v ol 0.4 v i ol = 8 ma od 12 - open - drain output pin with sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma od 48 - open - drain output pin with sink capability of 48 ma output low volt age v ol 0.4 v i ol = 48 ma in t - ttl level input pin input low voltage v il 0.8 v input high voltage v ih 2.0 v input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v in ts - ttl level schmitt - triggered input pin i nput low threshold voltage v t - 0.5 0.8 1.1 v v dd = 5 v input high threshold voltage v t+ 1.6 2.0 2.4 v v dd = 5 v hysteresis v th 0.5 1.2 v v dd = 5 v input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v
w83l 784r preliminary publication release date: oct. 1999 - 51 - revision 0.55 11.3 ac characteristi cs valid data scl sda in sda out t hd;sda t scl t hd;dat t su;sto t su;dat serial bus timing diagram serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup - up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold tim e t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns
w83l 784r preliminary publication release date: oct. 1999 - 52 - revision 0.55 12. how to read the top marking the top marking of W83L784R W83L784R 2826978y-61 814ob left: winbond logo 1st line: winbond logo and the type number: W83L784R 2 nd line: tracking code 2 826978y - 61 2 : wafers manufactured in winbond fab 2 826978y - 61 : wafer production series lot number 3rd line: tracking code 814 o b 814 : packages made in ' 98 , week 14 o : assembly house id; a means ase, s means spil, o means ose b : ic revision
w83l 784r preliminary publication release date: oct. 1999 - 53 - revision 0.55 13. package drawing and dimensions 20 ssop - 209 mil 1 2 d e e y b a1 a2 a seating plane dteail a l l1 q detail a seating plane e h 10 11 0 0.002 0.197 0.291 7.80 0 7.40 8 8.20 5.30 b e d c 6.90 5.00 a1 a2 a 5.60 7.50 7.20 2.00 1.85 8 0.323 0.307 0.073 0.079 0.220 0.272 0.295 0.283 0.209 min. dimension in inch symbol dimension in mm min. nom max. max. nom 0.05 e l l1 y q 0.009 0.015 0.004 0.010 0.021 0.030 0.050 0.004 0.22 0.38 0.09 0.25 0.65 0.0256 0.55 0.75 1.25 0.10 h e 0.95 0.037 1.75 1.65 0.065 0.069 headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the t rade marks of products and companies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.
14. W83L784R schematics 784ap.sch 0.5 W83L784R application circuit b 1 1 thursday, september 09, 1999 title size document number rev date: sheet of vcc fan5vcc fan5vcc fan5vcc fan5vcc 3vcc 3vsb vcc 3vcc vcc 3vcc cpu_vcore to piix4 voltage sensoring circuit temperature sensoring circuit note: 1. cput1 is for cpu1 temperature and smartfan 1 2. cput2 is for cpu2 temperature and smartfan 2 smartfan1 speed control circuit smartfan2 speed control circuit signal power gnd signal power gnd eg: pwmout1 is open-drain default. pwmout2 is open-drain default. rev. 0.1: ignore. when 784 is power-down, fan5vcc should be turned off. when 784 is power-down, fan5vcc should be turned off. up 0.2: W83L784R application circuit. 0.3: change pin5,pin6,pin11 to low active. change pin7 pull-up to 3vsb. 0.4: d1,d2,r9,r15 can be removed. (refer application notice 1) change r1 to 0 ohm. add r27,r28,r29,r30(reserved). pull-up 0.5: add a pull-up resistor r31. vcore +3.3vin vbat fanin1 fanin2 vt1/pii1 pwmout1 vt2/pii2 pwmout2 vref vcore smi# +3.3vin ovt# vbat scl sda vref vt1/pii1 vref vt2/pii2 pwmout1 fanin1 sda scl pwmout2 fanin2 r2 r 0 r3 r 0 r4 r 4.7k r5 r 4.7k r8 r 10k c1 cap 10u c2 cap 0.1u r9 10k r10 4.7k jp1 header 3 1 2 3 q1 3906 r11 1k r12 4.7k d1 1n4148 c3 47u + winbond electronics corp. r13 r 10k 1% rt1 thermistor 10k 1% t r14 r 30k 1% c4 cap 3300p r15 10k r16 4.7k jp2 header 3 1 2 3 q2 3906 r17 1k r18 4.7k d2 1n4148 c5 47u + r19 4.7k r20 4.7k r21 2k r22 2k r23 4.7k r24 4.7k u1 W83L784R fanin1/gpo1 1 fanin2/gpo2 2 pwmout1 3 pwmout2 4 fanfault#/gpo3 5 pwr_dn# 6 smi# 7 ovt# 8 scl 9 sda 10 vcc 20 cput1/pii1 19 cput2/pii2 18 vref 17 vin1 16 reset# 15 vin2(+3.3vin) 14 vin3(vbat) 13 gnd 12 batfault#/gpo4 11 q3 mosfet n q4 mosfet n bt1 battery dc 10v r25 r 99k r26 r 232k r1 r 0 r27 10k r6 4.7k r7 4.7k r28 10k r29 10k r30 10k r31 r 10k smclk smdat thrm# extsmi# piid+ piid- reset# reset# pwr_dn# fanfault# batfault# batfault# fanfault# pwr_dn#

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